This invention relates to a digital equalizer for high-speed serial communications, particularly in a high-speed serial interface of an integrated circuit device.
Many integrated circuit devices can be programmed. Examples of programmable integrated circuit devices include volatile and non-volatile memory devices, field programmable gate arrays (“FPGAs”), programmable logic devices (“PLDs”) and complex programmable logic devices (“CPLDs”). Other examples of programmable integrated circuit devices include application-specific integrated circuits (ASICs), processors and microcontrollers that are programmable via internal or external memory. Programmable integrated circuit devices, such as programmable logic devices (PLDs) in particular, frequently incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards. Higher data volumes demand high-speed, high-throughput data processing. Serial communication reduces the number of pins and parallel lines on a device and, therefore, reduces the overall cost of the device and reduces the problem of data skew in parallel lines by avoiding synchronous interfaces.
In such interfaces, many different signalling schemes may be used, including binary, Non-Return to Zero (NRZ), multi-level Pulse Amplitude Modulation (e.g., 4-PAM), and Duo-Binary. However, as data rates increase, particularly into the gigabit range, these may prove inadequate because of, e.g., inter-symbol interference (ISI)—due mostly to attenuation over long signal paths such as those that cross backplanes—as well as crosstalk. Attenuation is known to increase with frequency, and the changing data patterns as symbols change increase the effective frequency further, resulting in attenuation-induced ISI. Further, reflections at connectors and other terminations also may contribute to signal degradation.
Dispersion may be considered a major factor causing ISI. Data may have several frequency components, and attenuation in both backplanes and optical fiber is frequency-dependent. As a result, transmitted data having low-frequency content may arrive at the receiver at a slightly different time than data having higher-frequency content. Because in many high-speed serial systems, data are sent without a separate clock, the clock then must be extracted from the data using clock-data recovery (CDR) techniques. However, the foregoing time-of-flight differences introduce jitter (i.e., close the receive eye) which makes the process of recovering the data and clock harder. Therefore, CDR techniques may suffer as the foregoing effects degrade the received signal.
In optical fiber systems, optical dispersion is generally associated with chromatic and polarization dispersion phenomena, and correcting through equalization is often necessary and generally harder than correcting for backplane attenuation.
Various techniques have been developed in attempts to deal with these effects. Pre-Emphasis or De-Emphasis circuits may be used at the transmitter end, but the effect of pre-emphasis/de-emphasis may enhance crosstalk noise. “Equalization” techniques, including Feed-Forward Equalization (FFE) and analog Decision Feedback Equalization (DFE) may be used at the receiver end. These analog techniques are particularly adapted for dealing with ISI, but are limited in dealing with other effects, particularly optical nonlinear dispersion effects, and can be limited in scalability.